Hardware devices are employed within computer systems to assist in determining the availability of computer resources (i.e., a memory chip, a hard disk drive, etc.) which can only be controlled and accessed by one requesting device at a time. However, metastable conditions can exist when contention between requests from different devices occurs. Arbitrators (or arbiters) have been designed to reduce bus contention through flags (or other such means). However, arbitrators can enter metastable states during simultaneous requests. Conventional arbitrators can therefore enter an undecided state and remain for an indefinite period of time, causing undesirable results (i.e., a system crash or hang, etc.).
Referring to FIG. 1, a circuit 10 is shown illustrating a conventional arbitration circuit. The circuit 10 comprises a NAND gate 12, a NAND gate 14 and an interlock circuit 16. The NAND gate 12 receives the signal A and an output from the NAND gate 14. The NAND gate 14 receives a signal B and an output from the NAND gate 12. The interlock circuit 16 presents a signal OUTA and a signal OUTB in response to the signal from the NAND gates 12 and 14. The NAND gates 12 and 14 are implemented in a cross-coupled configuration. Therefore, the NAND gates 12 and 14 can enter a metastable condition.
Referring to FIG. 2, a timing diagram of the circuit 10 is shown. The input A and the input B are shown crossing between a time T1 and a time T2. The period between the time T1 and T2 illustrates the metastable event which can cause a push out. The circuit 10 is subject to metastability when the inputs A and B change states simultaneously.
The interlock circuit 16 attempts to resolve metastable states, but does not prevent metastable events. The arbitration circuit 10 implements cross coupled NAND arbiters (12 and 14) which cause delays due to metastable events. The resolution (or recovery) time of the cross coupled arbiters 12 and 14 is not predictable. While the interlock circuit 16 can try to prevent metastable states from occurring on the outputs, the interlock circuit 16 does not resolve the occurrence of the metastable events. Conventional arbitrators attempt to reduce the probability of metastable occurrences rather than eliminate such occurrences.
It is desirable to provide a method and/or architecture that provides multiport arbitration using phased locking arbiters.